VLSI Interview Preparation Guide
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Very-large-scale integration (VLSI) frequently Asked Questions by expert members with experience in VLSI. So get preparation for the Very-large-scale integration (VLSI) job interview

17 VLSI Questions and Answers:

1 :: Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine?

1.Instruction fetch
2.decode instruction and read register files
4.data to access from memory
5.write back

throughput is the total amount of work done in a given time,
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2 :: Explain How many bit combinations are there in a byte?

1 byte means 8 bits so 256 com
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3 :: Suppose For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

the purpose of cache is to reduce the average time to
access the main memory, the operation is like that when the
CPU wants to access the data, it first check the cache, if
an entry can be found with a tag matching that of desired
data, CPU gets the data from cache directly, otherwise, the
data will be copied into cache for next access.
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4 :: Do you know MESI?

Is a widely used cache coherency and memory coherence
protocol introduced by Intel. Modified Exclusive Shared
Invalid are the protocol States.

M means value has been modified from main memory and the
cache is required to write the data back to main memory,
before permitting any other read of the main memory state.

E IS CLEAN: Value Match with main memory

S Cache may be stored in other caches of the machine

I Invalid
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5 :: What are the main issues associated with multiprocessor caches and how might you solve them?

issue : Cache coherency or Data coherency. The problem is
all the processors cache should have exactly the same
shared data (cohenrent data). and there are races possible
with multiprocessors.

possible solution: use one central cache controller which
will get all the read/write requests from all the
processors and peripherals so that it can make sure there
are no races and cache coherency is maintained.
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