Electrical Engineering Interview Questions and Answers

1 :: What is the difference between a Verilog task and a Verilog function?

The following rules distinguish tasks from functions:
A function shall execute in one simulation time unit;
a task can contain time-controlling statements.
A function cannot enable a task;
a task can enable other tasks or functions.
A function shall have at least one input type argument and shall not have an output or inout type argument;
a task can have zero or more arguments of any type.
A function shall return a single value; a task shall not return a value.

Is This Answer Correct?    6 Yes 0 No

2 :: Given the following Verilog code, what value of "a" is displayed?

Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end


This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:

1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue.
Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.

Is This Answer Correct?    0 Yes 1 No

3 :: Given the following snipet of Verilog code draw out the waveforms for clk?

Given the following snipet of Verilog code, draw out the waveforms for clk and a
always @(clk) begin
a = 0;
#5 a = 1;
end

       10      30      50      70      90     110     130

        ___     ___     ___     ___     ___     ___     ___

clk ___|   |___|   |___|   |___|   |___|   |___|   |___|   |___





a   ___________________________________________________________

This obviously is not what we wanted, so to get closer, you could use
"always @ (posedge clk)" instead, and you'd get

       10      30      50      70      90     110     130

        ___     ___     ___     ___     ___     ___     ___

clk ___|   |___|   |___|   |___|   |___|   |___|   |___|   |___



                            ___                     ___

a   _______________________|   |___________________|   |_______

Is This Answer Correct?    1 Yes 1 No

4 :: What is the difference between the following two lines of Verilog code?

What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;


#5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units hence.

a = #5 b; The value of b is calculated and stored in an internal temp register.
After five time units, assign this stored value to a.

Is This Answer Correct?    1 Yes 0 No

5 :: What is the difference between:
c = foo ? a : b;
and
if (foo) c = a;
else c = b;

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x.
On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

Is This Answer Correct?    1 Yes 0 No