Electrical Engineering Interview Preparation Guide
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Electrical engineering interview questions and answers, referred to as electrical and electronic engineering, Electrical Engineering interview questions and answers guide deals with the study and application of electricity, electronics and electromagnetism. The field interview questions and answers first became an identifiable occupation in the late nineteenth century after commercialization of electric telegraph and electrical power supply. Learn Electrical Engineering by interview questions

104 Electrical Engineering Questions and Answers:

1 :: What is the difference between a Verilog task and a Verilog function?

The following rules distinguish tasks from functions:
A function shall execute in one simulation time unit;
a task can contain time-controlling statements.
A function cannot enable a task;
a task can enable other tasks or functions.
A function shall have at least one input type argument and shall not have an output or inout type argument;
a task can have zero or more arguments of any type.
A function shall return a single value; a task shall not return a value.
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2 :: Given the following Verilog code, what value of "a" is displayed?

Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end


This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:

1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue.
Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.
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3 :: Given the following snipet of Verilog code draw out the waveforms for clk?

Given the following snipet of Verilog code, draw out the waveforms for clk and a
always @(clk) begin
a = 0;
#5 a = 1;
end

10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___


a ___________________________________________________________


This obviously is not what we wanted, so to get closer, you could use
"always @ (posedge clk)" instead, and you'd get


10 30 50 70 90 110 130
___ ___ ___ ___ ___ ___ ___
clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___
a _______________________| |___________________| |_______

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4 :: What is the difference between the following two lines of Verilog code?

What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;


#5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units hence.

a = #5 b; The value of b is calculated and stored in an internal temp register.
After five time units, assign this stored value to a.
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5 :: What is the difference between:
c = foo ? a : b;
and
if (foo) c = a;
else c = b;

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x.
On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.
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6 :: Using the given, draw the waveforms for the following versions of a?

Using the given, draw the waveforms for the following versions of a (each version is separate, i.e. not in the same run):
reg clk;
reg a;

always #10 clk = ~clk;

(1) always @(clk) a = #5 clk;
(2) always @(clk) a = #10 clk;
(3) always @(clk) a = #15 clk;

Now, change a to wire, and draw for:

(4) assign #5 a = clk;
(5) assign #10 a = clk;
(6) assign #15 a = clk;
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7 :: What is the difference between running the following snipet of code on Verilog vs Vera?

What is the difference between running the following snipet of code on Verilog vs Vera?

fork {
task_one();
#10;
task_one();
}

task task_one() {
cnt = 0;
for (i = 0; i < 50; i++) {
cnt++;
}
}
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8 :: Write the code to sort an array of integers?

/* BEGIN C SNIPET */

void bubblesort (int x[], int lim) {
int i, j, temp;

for (i = 0; i < lim; i++) {
for (j = 0; j < lim-1-i; j++) {

if (x[j] > x[j+1]) {
temp = x[j];
x[j] = x[j+1];
x[j+1] = temp;

} /* end if */
} /* end for j */
} /* end for i */
} /* end bubblesort */

/* END C SNIPET */

Some optimizations that can be made are that a single-element array does not need to be sorted; therefore, the "for i" loop only needs to go from 0 to lim-1. Next, if at some point during the iterations, we go through the entire array WITHOUT performing a swap, the complete array has been sorted, and we do not need to continue. We can watch for this by adding a variable to keep track of whether we have performed a swap on this iteration.
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9 :: Write the code for finding the factorial of a passed integer. Use a recursive subroutine?

// BEGIN PERL SNIPET

sub factorial {
my $y = shift;
if ( $y > 1 ) {
return $y * &factorial( $y - 1 );
} else {
return 1;
}
}

// END PERL SNIPET
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10 :: In C, explain the difference between the & operator and the * operator?

& is the address operator, and it creates pointer values.
* is the indirection operator, and it preferences pointers to access the object pointed to.

Example:
In the following example, the pointer ip is assigned the address of variable i (&i). After that assignment, the expression *ip refers to the same object denoted by i:

int i, j, *ip;
ip = &i;
i = 22;
j = *ip; /* j now has the value 22 */
*ip = 17; /* i now has the value 17 */
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