# Hardware Design Question: **Download Questions PDF**

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## What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

## Answer:

Suppose your flip-flop is positive edge triggered. time for which data should be stable prior to positive edge clock is called setup time constraint .

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

if any of these constraints are violated then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:

1. Tcq + Tcomb> Tskew + Thold

2. Tcq + Tcomb<Tskew +T - Tsetup

Tcq is time delay when data enters the flip-flop and data comes at output of flip flop.

Tcomb is the logic delay between two flip flop.

Tskew is the delay of clock to flip flop: suppose there are two flip flop ,if clock reaches first to source flip flop and then after some delay to destination flip flop ,it is positive skew and if vice versa then negative skew.

so if you take 2 eq you will see that setup time is the determining factor of clock's time period.

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

if any of these constraints are violated then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:

1. Tcq + Tcomb> Tskew + Thold

2. Tcq + Tcomb<Tskew +T - Tsetup

Tcq is time delay when data enters the flip-flop and data comes at output of flip flop.

Tcomb is the logic delay between two flip flop.

Tskew is the delay of clock to flip flop: suppose there are two flip flop ,if clock reaches first to source flip flop and then after some delay to destination flip flop ,it is positive skew and if vice versa then negative skew.

so if you take 2 eq you will see that setup time is the determining factor of clock's time period.

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